The present invention relates to a semiconductor integrated circuit comprising a boosted power supply generating circuit which supplies charges to an internal boosted power supply in a DRAM or the like.
Recently, the capacity of a dynamic RAM (hereinafter referred to as a DRAM) has been increased so that the area of a semiconductor chip has become greater. An increase in chip size is the minus factor of a gain in speed of the access time of the DRAM. A continuous boosting method has been employed as the technology for realizing the gain in speed of the DRAM. The continuous boosting method serves to increase the speed of the operation of the DRAM and is very effective in the extension of a pause time, the enlargement of an operating margin during sense and the like by setting the level of a word line to a boost level in the same manner as a boosting method according to the prior art.
For example, Japanese Laid-Open Patent No. 4-301998 has disclosed the boost technology using the continuous boosting method.
An example of a boosted power supply generating circuit according to the prior art will be described below with reference to the drawings. FIG. 13 is a block diagram schematically showing a boosted power supply generating circuit 100 according to the prior art. In FIG. 13, 101 designates a level detecting circuit, 102 designates an oscillating circuit, 103 designates a sub-boosted power supply generating circuit, 104 and 105 designate a main boosted power supply generating circuit and a potential limiting circuit for operating on receipt of a low address strobe signal (hereinafter referred to as XRAS) respectively, and 106 designates a boosted power supply. The sub-boosted power supply generating circuit 103 continuously operates so as to hold the voltage level of the boosted power supply 106 to a proper level during the standby of a DRAM. In order to reduce power consumption during the standby, a charge supply capability is set lower. The main boosted power supply generating circuit 104 operates only during the operation of the DRAM. A lot of circuits connected to the boosted power supply 106 operate during the operation of the DRAM so that the charges of the boosted power supply 106 are consumed. Consequently, the charge supply capability of the main boosted power supply generating circuit 104 is set higher.
FIG. 9 is an electric circuit diagram showing the detailed structure of the level detecting circuit 101, the oscillating circuit 102 and the sub-boosted power supply generating circuit 103 shown in FIG. 13. As shown in FIG. 9, the level detecting circuit 101 is connected to the oscillating circuit 102 by a control signal line 143 for transmitting a control signal. The control signal line 143 is connected to an input terminal 142 and a node 110 of the level detecting circuit 101 through a NAND circuit. The oscillating circuit 102 is connected to the sub-boosted power supply generating circuit 103 through signal lines 145 and 146. The sub-boosted power supply generating circuit 103 is connected to the level detecting circuit 101 through the boosted power supply 106.
The level detecting circuit 101 generates a control signal for controlling the oscillating circuit 102 based on the voltage level of the boosted power supply 106. The control signal is input to the oscillating circuit 102 through the node 110 and the signal line 143. A NAND circuit, an inverter, a MOS transistor, a NOR circuit and the like are provided in the oscillating circuit 102. The oscillating circuit 102 operates on receipt of the control signal sent from the level detecting circuit 101.
The circuit shown in FIG. 9 has a structure in which an input to the input terminal 142 is set to the "H" level, the voltage level of the boosted power supply 106 is detected by the level detecting circuit 101, and the result thus obtained is reflected in the voltage level (H or L) of the control signal line 143 so that the operation and non-operation of the oscillating circuit 102 are controlled. If the voltage level of the boosted power supply 106 is higher than a set voltage level, the output signal of the node 110 of the level detecting circuit 101 has the "L" level. Consequently, the control signal of the control signal line 143 sent to the oscillating circuit 102 has the "L" level so that the oscillating circuit 102 does not operate. Accordingly, an oscillating signal is not input to the signal lines 145 and 146 so that the subboosted power supply generating circuit 103 does not operate. On the contrary, if the voltage level of the boosted power supply 106 is lower than the set voltage level, the output signal of the node 110 of the level detecting circuit 101 has the "H" level. Accordingly, the control signal of the control signal line 143 has the "H" level so that the oscillating circuit 102 operates. Then, the sub-boosted power supply generating circuit 103 operates so that an oscillating signal is output to the signal lines 145 and 146. The voltage level of the internal side plate of a capacitor 131 (or the internal side plate of a capacitor 132) of the sub-boosted power supply generating circuit 103 is boosted by the voltage level of the capacitor 131 (or the capacitor 132) in response to the. oscillating signal so that charges are supplied to the boosted power supply 106 through a boost power line 147. Consequently, the voltage level of the boosted power supply 106 is boosted.
Recently, members forming an element have become thinner remarkably with the finer structure of the DRAM. For this reason, the potential limiting circuit 105 shown in FIG. 13 is provided in order to limit a voltage applied to the element and ensure the responsibility of the element. The potential limiting circuit 105 limits the voltage level of the boosted power supply 106 to a voltage level which is higher than a predetermined first power level by the threshold voltage of a memory cell transistor.
FIG. 10 is a circuit diagram for explaining the operation of the potential limiting circuit 105. As shown in FIG. 10., the potential limiting circuit 105 comprises a level shift portion 151 and a charge drawing portion 152. A control signal is input to the level shift portion 151 through an input terminal 153. An output which is level-converted by the level shift portion 151 is input to the charge drawing portion 152 through a signal line 154. An NMOS transistor 155 having a threshold voltage which is almost equal to that of the memory cell transistor is provided on the charge drawing portion 152. The NMOS transistor 155 is provided between the boosted power supply 106 and a first power source 156, and the gate of the NMOS transistor 155 is connected to the signal line 154. When the control signal input from the input terminal 153 has the "L" level, the output of the level shift portion 151 is set to the voltage level of the boosted power supply 106, the NMOS transistor 155 is turned ON, and the charges of the boosted power supply 106 are drawn to the first power source 156 so as to lower the voltage level of the boosted power supply 106 to a voltage level (set value) which is higher than the voltage level of the first power source 156 by the threshold voltage of the NMOS transistor 155. It is concerned that the voltage level of the first power source 156 is varied by drawing the charges toward the first power source 156. However, circuits for consuming the charges are connected to the first power source 156 and operates to consume the charges so that the voltage level is kept stable.
The general operation of the boosted power supply generating circuit 100 having each portion formed in the above manner will be described below with reference to FIG. 13 and the like.
When XRAS has the "H" level, that is, during the standby of the DRAM, the oscillating circuit 102 operates on receipt of a signal output from the level detecting circuit 101 so that the sub-boosted power supply generating circuit 103 is driven if the voltage level of the boosted power supply 106 is lower than the detection level of the level detecting circuit 101. Consequently, the charges are supplied to the boosted power supply 106 so that the voltage level of the boosted power supply 106 is boosted. If the voltage level of the boosted power supply 106 is higher than the detection level, the oscillating circuit 102 does not operate. Consequently, the sub-boosted power supply generating circuit 103 is not driven. In this case, the main boosted power supply generating circuit 104 and the potential limiting circuit 105 do not operate.
When XRAS is changed from the "H" level to the "L" level, that is, during the operation of the DRAM, the main boosted power supply generating circuit 104 is driven synchronously with the fall of XRAS. Consequently, the charges are supplied to the boosted power supply 106 so that the voltage level of the boosted power supply 106 is boosted. Consequently, the potential of a word line connected to the gate of the memory cell transistor which stores information is caused to rise. The main boosted power supply generating circuit 104 is driven only synchronously with the fall of XRAS. Hence, the main boosted power supply generating circuit 104 does not have the function of holding the voltage level of the boosted power supply 106. Accordingly, the sub-boosted power supply generating circuit 103 is caused to operate also during the operation of the DRAM so that the charges are supplied to the boosted power supply 106 to hold the voltage level. The main boosted power supply generating circuit 104 has the high charge supply capability. For this reason, there is a possibility that the voltage level of the boosted power supply 106 is increased too much. Consequently, the potential limiting circuit 105 is caused to operate synchronously with the fall of XRAS so that the charges of the boosted power supply 106 are drawn while XRAS has the "L" level. Thus, the voltage level of the boosted power supply 106 is lowered to a set value.
The operation of the output circuit of the DRAM connected to the boosted power supply 106 and the like will be described below with reference to FIG. 11.
As shown in FIG. 11, a control circuit 181 for outputting a control signal S2 on receipt of XRAS, a column address strobe signal (hereinafter referred to as XCAS), an output enable signal (hereinafter referred to as XOE) and a write enable signal (hereinafter referred to as XWE), a NAND circuit 183 for executing the NAND operation of the control signal S2 and an output data signal, and an AND circuit 184 for executing the AND operation of the control signal S2 and the inverted output data signal are provided on the input side of a boost circuit 182. An output circuit 108 is provided on the output side of the boost circuit 182. The output circuit 108 comprises NMOS transistors 185 and 186 connected between a first power source and a ground power source. The NMOS transistor 185 is controlled by the output of the boost circuit 182. The NMOS transistor 186 is controlled by the output of the AND circuit 184. Data is output to an output terminal 189 connected between the NMOS transistors 185 and 186.
FIG. 12 is a circuit diagram showing the internal structure of the boost circuit 182 in FIG. 11. The output of the NAND circuit 183 is sent to an input terminal 201 of the boost circuit 182. The input terminal 201 is connected to one of the electrodes of a capacitor 205 through an inverter 202, a delay circuit 203 and an inverter 204. The other electrode of the capacitor 205 is connected to an output terminal 208 for outputting a control signal to the NMOS transistor 185 of an output circuit. An NMOS transistor 206 is provided between the input terminal 201 and the output terminal 208. The gate electrode of the transistor 206 is connected to a first power source. Furthermore, an NMOS transistor 207 is provided between the input terminal 201 and the output terminal 208. The output of the inverter 202 is sent to the gate electrode of the transistor 207.
In the boost circuit 182 shown in FIG. 12, the output signal is set to the "L" level by the operation of the transistor 207 when the input signal has the "L" level. On the other hand, when the input signal is changed from the "L" level to the "H" level, the voltage level of the output signal is raised to the voltage level -Vth of the first power source by the operation of the transistor 206, wherein Vth is the threshold voltage of the transistor 206.
At this moment, the output of the inverter 204 has the "L" level. For this reason, the capacitor 205 is charged to VDD-Vth. After a delay time determined by the delay circuit 203, the inverter 204 raises the potential of one of the electrodes of the capacitor 205. Consequently, the voltage level of an output signal is set to VDD+.alpha. (.alpha.&gt;0). In other words, when a signal input to the boost circuit 182 is set to the "H" level, the output signal of the boost circuit 182 is set to a higher boost level than that of the input signal.
Referring to the circuit shown in FIG. 11, when the data reading operation is determined, the gate of the NMOS transistor 185 is set to the "L" level by the boost circuit 182 and the gate of the NMOS transistor 186 is set to the "H" level by the AND circuit 184 if an output data signal has the "L" level. Accordingly, the NMOS transistor 185 is turned OFF and the NMOS transistor 186 is turned ON so that Low data is output to the output terminal 189. If the output data signal has the "H" level, the gate of the NMOS transistor 185 is set to a boost level by the boost circuit 182 and the gate of the NMOS transistor 186 is set to the "L" level by the AND circuit 184. Accordingly, the NMOS transistor 185 is turned ON and the NMOS transistor 186 is turned OFF so that High data is input to the output terminal 189.
When outputting the High data, the following problems arise if the gate of the NMOS transistor 185 is not set to a boost voltage. When setting the voltage level of the first power source to VDD and outputting the High data, only the voltage level VDD-Vth is output to the output terminal 189 if the voltage level of the gate of the NMOS transistor 185 is VDD and the threshold voltage of the NMOS transistor 185 is set to Vth. In the case where the potential of the gate of the NMOS transistor 185 is set to a boost voltage VDD+Vth, the voltage level of the output terminal 189 is set to a voltage level of VDD+Vth-Vth=VDD so that the sufficient High data can be obtained. In the output circuit of the DRAM, thus, the gate terminal of the NMOS transistor 185 is set to the boost voltage so that the sufficient High data can be output when reading the High data.
However, the above structure has the following problems.
A first problem will be described below. When XRAS has the "L" level, that is, in operation mode, a junction leak current and a transistor off leak current are generated on a junction portion and a transistor connected to the boosted power supply 106. Consequently, if charge consumption exceeds the charge supply capability of the sub-boosted power supply generating circuit 103, the voltage level of the boosted power supply 106 is gradually decreased. In particular, when the period for which XRAS has the "L" level is longer, the voltage level of the boosted power supply 106 is greatly lowered because the charges are not supplied from the main boosted power supply generating circuit 103. For this reason, there is a possibility that a malfunction occurs to a circuit due to the restore of information in the XRAS cycle, the shortage of a write voltage and the shortage of a read voltage in the next XRAS cycle.
A second problem will be described below. When the potential limiting circuit 105 operates synchronously with the fall of XRAS, the charges are drawn from the boosted power supply 106 before the charges of the boosted power supply 106 are consumed by the rise of the word line. For this reason, when or after the word line rises, the charges should be supplied to the boosted power supply 106 again. Consequently, there is a possibility that useless power consumption is increased or the rising operation of the word line is delayed.
A third problem will be described below. When reading the data, the gate terminal of the NMOS transistor 185 of the output circuit 108 is boosted after the reading operation is determined and it is decided that the output data is High data. In addition, the boost circuit has a delay circuit. Consequently, it takes a long time to read the High data.